Nonvolatile memory is well known in the art. The different types of NVM include mask ROM, EPROM, EEPROM, NOR and NAND flash memories. In this invention, the terms NOR, NOR flash, and NOR memory are interchangeable used to generally refer to the NOR flash memories, and the same applies to the NAND flash memory. The VM includes DRAM and SRAM. DRAM cell has one transistor connected in series with one capacitor but SRAM cell is always comprised of a 6-transistor cell which is quite large in the silicon area used on a chip. In general, the cost of NAND memory is much cheaper than NOR memory and SRAM because a NAND cell has the smallest cell size with 4λ2 (λ being a minimum feature size in a semiconductor process) for storing two single-level cell (SLC) binary data. The highest NAND memory density available today is 64 Gbs per chip with multi-level cell (MLC) storage by using 30 nm technology node. For a conventional ETOX™-based NOR cell, the cell size is about 12-16λ2 and is becoming more and more difficult to be scaled down below 45 nm technology. The highest density of NOR flash is 1 Gbs using 32 nm process. The cell size of SRAM is always the largest one due to its 6-transistor cell with about 160λ2 and therefore the highest density of SRAM is only around 64 Mb using 32 nm technology with about 7 to 8 metal layers.
FIG. 1A is a plane layout view of a conventional 1T 2-poly, floating-gate type NMOS NAND flash cell. Only three key cell's connection terminals of Drain (N-active), Source (N-active) and Gate (Poly2) are shown and denoted as “D”, “S” and “G” respectively. A schematic symbol for the circuit corresponding to the NAND cell of FIG. 1A is shown in FIG. 1B. The circuit is a three-terminal, NMOS, 2-poly, floating-gate NAND cell. Three nodes for the drain, source and gate of the NAND cell are shown in the circuit. The other three nodes of the NAND cell include nodes for the triple P-well (TPW), deep N-well (DNW) and P-substrate (PSUB) are not shown in the schematic symbol.
FIG. 1C shows a cross sectional view of the NMOS NAND cell according to FIG. 1A. The floating-gate gate is made of a poly1 conduction layer right underneath a poly2-gate. The poly2-gate is denoted as “G.” All six nodes (D, G, S, TPW, DNW and PSUB) of a single NAND cell have to be coupled with appropriate bias conditions in the circuit for respective operations. The poly1 node is a floating-node and therefore it has no external terminal for circuit connection. Poly1 is not accessible from the circuit.
FIG. 1D shows a chart of two typical wide Vt distributions of a conventional SLC NAND cell according to FIG. 1A. Two Vts include the first negative erased state of Vt0 with a center value of −2.0V and a variation of 2V, varying from −1.0V to −3.0V and the second positive programmed state of Vt1 with a center value of +2.0V and a variation of 2V, varying from +1.0V to +3.0V. A single physical NAND cell that stores 2-Vt is referred to as a 1b1T SLC NAND cell.
FIG. 1E shows another chart of four Vt distributions of a typical NAND cell according to FIG. 1A. Four Vts include the first negative erased state of Vt0 with a wide Vt distribution with a center value of −2.0V and a variation of 2V, varying from −1.0V to −3.0V, the second positive programmed state of Vt1 with a center value of +0.75V and a variation of 0.5V, varying from +0.5V to +1.0V, the third positive programmed state of Vt2 with a center value of +1.75V and a variation of 0.5V, varying from +1.5V to +2.0V and the fourth positive programmed state of Vt3 with a center value of +2.75V and a variation of 0.5V, varying from +2.5V to +3.0V. The three positive programmed states of Vt1, Vt2 and Vt3 are programmed states with a narrow distribution for a proper MLC operation. A NAND cell that stores four Vts is referred to as a 2b1T MLC NAND cell.
In recent years, usage and application of multiple types of NVM in one single-chip combo flash IC design are emerging in embedded CPU systems. A combo-type flash design that integrates NAND, NOR, EEPROM into one single-chip to save the board size, power consumption and overall system cost has found a big market in the semiconductor industry. Because NAND memory has the smallest cell size and most economical process, it is always desirable to use the NAND process to manufacture NOR and SRAM so that the highest integration of NVM and VM in one chip can be realized in a lowest manufacturing cost. However, in the conventional semiconductor technology, NAND, NOR and SRAM are not compatible in process and cannot be integrated into one chip.
SRAM memory can be made of low-voltage PMOS and NMOS devices in NAND or NOR process but it is not economical due to many high-voltage process steps involved in the conventional NOR and NAND. In practice, the real bottleneck to integrate the three different types of volatile and non-volatile memories in one chip is to integrate the two different types of non-volatile memories, i.e., NAND and NOR, in one chip. This is because NAND and NOR processes and cell operations are quite different in the conventional technology. If NAND and NOR can be fully integrated in one chip, then SRAM can always be integrated subsequently although the block size and speed performance of SRAM may not be best optimized.
Traditionally, the mainstream NAND and NOR cells are made of 2-poly floating-gate NMOS devices to store electrons for respective data and code storage. Both NAND and NOR cells are formed in a triple P-well within a deep N-well on top of a P-substrate. NOR cell operations such as erase and program are performed by using +/−10V. Therefore, the peripheral high voltage (HV) devices of NOR cells are tuned to sustain +/−10V drain breakdown voltage (BVDS). The peripheral process of NOR has triple P-wells for making HV NMOS to provide the negative high-voltage up to −10V. However, NAND cell operations use +20V without requiring any negative HV. As a result, the peripheral process of NAND does not need to have any triple P-well device for generating any negative HV. In summary, because of the very different HV requirements in cell operations described above, NAND and NOR processes are not made compatible at all.
In addition, during a program operation, the drain-to-source voltage (Vds) of a NOR cell has to be kept around +5.0V for channel hot electron injection (CHE) high current byte program. Due to this CHE scheme, the cell's channel length is very difficult to be scaled down below 65 nm. On the contrary, the program and erase operations of NAND cells require Vds=0V and the read operation requires Vds=1.0V. Therefore, the channel length of a NAND cell has been highly scaled down with a constant cell size of 4λ2 below 30 nm to manufacture a 64 Gb die with MLC storage.
There are several so-called combo flash designs in the market in recent years. Mainly, these combo-type NVM chips cover the integration of NAND and NOR with an objective of providing both code and data storages in one single flash memory device. In reality, however, neither true NAND nor true NOR has been realized due to the incompatible process of the conventional NAND and NOR flash memories.
The first kind of so-called combo NVM chips to store both data and code was introduced by Samsung's OneNAND™ flash. This chip design is not really a genuine combo type of NOR and NAND flashes. In fact, within an OneNAND™ chip, there exists only one type of NVM core memory, i.e., NAND, along with 16 KB SRAMs. There is no provision of true NOR memory inside the OneNAND™ chip. OneNAND™ achieves faster partial-random read than a regular NAND but is slower than a regular NOR. In short, Samsung OneNAND™ is a 1-die chip made of NAND and SARM along with a pseudo NOR interface. It is not a combo flash chip made of NAND and NOR. Its speed has been improved over the raw NAND but it is still slower than the real NOR. In addition, OneNAND™ is not a full random access NOR memory.
The second combo NVM chip that can store both data and code in one chip was proposed by Spansion in its old ORNAND™ scheme and new Eclipse™ flash architecture in 2008. Neither ORNAND™ nor Eclipse™ is a combo flash that integrates real NAND and NOR. In reality, the ORNAND™ architecture is disadvantageous because of the lack of an on-chip NAND memory to provide features of low bit-cost, fast and low-current write, and better cell scalability. Although Eclipse™ may use 4b1T (Quad-bit) to compete against MLC 2b1T NAND, its basic cell size is larger than NAND. It also requires an extra large overhead in array and peripheral area and has inferior P/E endurance cycles. In fact, ORNAND™ and Eclipse™ should not be referred to as a combo NVM chip design. It should be considered as a NOR flash memory for storing hybrid data.
A real combo NVM array architecture comprising NAND, NOR and EEPROM in one single IC chip using one unified 1T NAND flash process was first disclosed by the original NAND flash inventor, Toshiba. For example, the U.S. Pat. No. 7,333,766 of Toshiba discloses several combo NVM flash arrays integrating three NVMs of NAND, NOR and EEPROM in one chip. The basic idea of Toshiba's combo flash solution is to use a unified 1T NAND cell structure and process for building a 2T NOR array and a 3T or 4T EEPROM cell and array. The beauty of Toshiba's combo flash approaches is no need of any change in NAND process.
Like all other regular NAND flash memories available today, Toshiba's NAND is comprised of a plurality of NAND strings. Each NAND string has one top NMOS Select transistor, one bottom NMOS Select transistor and a string of 32 NAND cells sandwiched in between top and bottom Select transistors. These two Select transistors become a big overhead of a regular NAND string. It is because every 32 NAND cells need 2 Select transistors These two Select transistors require a high voltage and are un-scalable because of the need to sustain a bulk-erase voltage of 20V and a bit-line program inhibit voltage of 10V. The channel length of each Select transistor is almost 3 times of that of a NAND cell. In addition, these two Select transistors are physically formed near the top word line and bottom word line cells. Poly1 and Poly2 have to be shorted at appropriate array locations to make Select transistors as Poly-1 non-floating-gate devices. The process complexity and high risk of device breakdown in program and erase operations due to thin Poly-1 gate oxide thickness are the drawbacks of the traditional NAND sting.
In the 2T NOR cell proposed by Toshiba, each 2T NOR cell is comprised of two NMOS transistors and can only store 1-bit SLC data. It is referred to here as a 1b2T NOR cell in this description. The top transistor of this 2T NOR cell is a 1T floating-gate 2-poly NAND cell and the bottom transistor is a regular NMOS 1-poly Select transistor. Only the top 1T NAND cell has the capability to store code data. The bottom NMOS Select transistor acts as a device switch offering no storage usage. Therefore, the overhead of this 2T NOR cell is one Select transistor per NAND cell. In summary, each Toshiba's 2T NOR cell can store only 1-bit SLC (1b2T) data or 2-bit MLC (2b2T) data. Therefore, it has difficulty competing with Intel's 1b1T regular SLC NOR cell or 2b1T MLC Strataflash™ cell. Similarly, the 3T EEPROM cell proposed by Toshiba comprises one 2-poly floating-gate NAND cell with two 1-poly regular Select transistors. Therefore, the overhead is even higher than its 2T NOR cell.
In summary, the Toshiba's newly proposed combo flash architecture, i.e., 1T NAND, 2T NOR and 3T EEPROM, has the advantage that all three NVMs are using the same NAND process and the same 1T NAND cell structure. Therefore, NAND, NOR and EEPROM use the same erase and program schemes of Fowler-Nordheim (FN) tunneling. Thus, the design and process and unit cell structures are unified for this combo flash architecture. The Toshiba's solution is most suitable for Gb-density NAND, Mb-density (less than 128 Mb) NOR and low-density (greater than 1 Mb) EEPROM combo NVM applications.